1. Field of the Invention
The invention relates in general to a thin-film transistor (TFT) array and associated display panel, and more particularly to a dot inversion dual gate TFT array and associated LCD panel.
2. Description of the Related Art
FIG. 1 shows a schematic diagram of a conventional LCD panel. The LCD panel comprises a TFT array 100, a gate driver 120, a source driver 110, and a timing controller 130. The gate driver 120 and the source driver 110 control a plurality of dot units in the TFT array. The dot units are categorized into red dot units R, green dot units G, and blue dot units B. A combination of one red dot unit R, one green dot unit B, and one blue dot unit B forms a single pixel. The timing controller 130 generates a first timing control signal T1 to the gate driver 120, and a second timing control signal T2 to the source driver 110. Timings of gate driving signals and brightness signals respectively generated by the gate driver 120 and the source driver 110 are controlled by the timing controller 130.
Taking a 1280×768 resolution TFT array 100 for example, the TFT array 100 comprises 1280×768 pixels, i.e., each row of the TFT array is consisted of 1280 pixels. Therefore, the source driver 110 comprises 3840 (i.e., 1280×3) data lines respectively providing brightness signals to 3840 dot units.
The source driver 120 comprises 768 gate lines that in sequence generate gate driving signals to assert the 3840 dot units of corresponding rows. More specifically, in order to display a frame on the TFT array 100, there are 768 cycles, within each of which one gate line is asserted. There are 3840 dot units on one row for receiving brightness data of 3840 data lines. Accordingly, after 768 cycles, corresponding brightness signals are received by all dot units so as to display a complete frame.
To prolong a lifespan as well as reducing residual images of an LCD panel, it is desired that images be displayed on a TFT array using a dot inversion approach.
FIG. 2 shows a schematic diagram for controlling a conventional TFT array when displaying a frame. Each dot unit comprises a switch device and a transparent electrode. A control end of the switch device is coupled to and controlled by a gate line. When the switch device is closed, the transparent electrode is connected to a corresponding data line. Conversely, when the switch device is open, the transparent electrode is disconnected from the data line. For example, the transparent electrode is an indium tin oxide (ITO) electrode. The switch device is a TFT having its gate coupled to the gate line, whereas the TFT has its two other ends respectively coupled to the data line and the ITO electrode.
With reference to FIG. 2, an (n−1) gate line (Gn−1) is connected to a control end of an (n−1, m−1) dot unit, an (n−1, m) dot unit, and an (n−1, m+1) dot unit. An TFT M(n−1, m−1) is connected between an (m−1)th data line Dm−1 and an ITO electrode I(n−1, m−1); an TFT M(n−1, m) in the (n−1, m) dot unit is connected between an (m)th data line Dm and an ITO electrode I(n−1, m); and an TFT M(n−1, m+1) in the (n−1, m+1) dot unit is connected between an (m+1)th data line Dm+1 and an ITO electrode I(n−1, m+1).
Further, an nth gate line Gn is connected to a control end of an (n, m−1) dot unit, an (n, m) dot unit, and an (n, m+1) dot unit. An TFT M(n, m−1) in the (n, m−1) dot unit is connected between an (m−1) data line (Dm−1) and an ITO electrode I(n, m−1); an TFT M(n, m) in the (n, m) dot unit is connected between an (m) data line (Dm) and an ITO electrode I(n, m); and an TFT M(n, m+1) in the (n, m+1) dot unit is connected between an (m+1) data line (Dm+1) and an ITO electrode I(n, m+1).
Further, an (n+1)th gate line Gn+1 is connected to a control end of an (n+1, m−1) dot unit, an (n+1, m) dot unit, and an (n+1, m+1) dot unit. An TFT M(n+1, m−1) in the (n+1, m−1) dot unit is connected between an (m−1) data line Dm−1 and an ITO electrode I(n+1, m−1); an TFT M(n+1, m) in the (n+1, m) dot unit is connected between an mth data line Dm and an ITO electrode I(n+1, m); and an TFT M(n+1, m+1) in the (n+1, m+1) dot unit is connected between an (m+1) data line (Dm+1) and an ITO electrode I(n+1, m+1).
As shown in FIG. 2, during an (n−1)th cycle Tn−1 when displaying a frame, the gate line Gn−1 is asserted. At this point, the data line Dm−1 provides brightness data of +a1 that is transmitted to the ITO I(n−1, m−1), the data line Dm provides brightness data of −a2 that is transmitted to the ITO I(n−1, m), and the data line Dm+1 provides brightness data +a3 that is transmitted to the ITO I(n−1, m+1).
Similarly, during an nth cycle Tn when displaying a frame, the gate line Gn is asserted. Meanwhile, the data line Dm−1 provides brightness data of −b1 that is transmitted to the ITO I(n, m−1), the data line Dm provides brightness data of +b2 that is transmitted to the ITO I(n, m), and the data line Dm+1 provides brightness data −b3 that is transmitted to the ITO I(n, m+1).
Similarly, during an (n+1)th cycle Tn+1 when displaying a frame, the gate line Gn+1 is asserted. Meanwhile, the data line Dm−1 provides brightness data of +c1 that is transmitted to the ITO I(n+1, m−1), the data line Dm provides brightness data of −c2 that is transmitted to the ITO I(n+1, m), and the data line Dm+1 provides brightness data +c3 that is transmitted to the ITO I(n+1, m+1).
To achieve dot inversion of a TFT array, it is necessary that brightness signals of neighboring data lines on the source driver have opposite polarities, and polarities of brightness signals on one data line need to be appropriately adjusted. Accordingly, when the TFT array 100 displays a frame, the (n, m) dot unit is positive (+) while its neighboring dot units are negative (−); this is referred to as dot inversion.
FIG. 3 shows a schematic diagram showing signals of a conventional TFT array with virtual dot inversion. During an (n−1)th cycle Tn−1, polarities of the first data line to the last data line are in sequence {(+), (−), (+), (−), . . . , (+), (−)}. During an nth cycle Tn, polarities of the first data line to the last data line are in sequence {(−), (+), (−), . . . , (−), (+)}. During an (n+1)th cycle Tn+1, polarities of the first data line to the last data line are in sequence {(+), (−), (+), (−), . . . , (+), (−)}, and so forth.
Due to the increase in the size of LCD panels, the number of data lines on a source driver also gets larger and larger. Therefore, to reduce the amount of data lines on a source driver, a dual gate TFT array is proposed. Taking a 1280×768 resolution TFT array for example, the number of data lines of a source driver is halved to 1920 and the number of gate lines of a gate driver is doubled to 1536 in a dual gate TFT array compared to those in the TFT array shown in FIG. 1.
Nevertheless, a driving method associated with the prior art applied to a dual gate TFT array is incompetent in achieving complete dot inversion.